simontemplar09
Cobragt is right each SPE has it's own local memory that operates a little differently then conventional cache.
for a good explanation on it:
http://www.blachford.info/computer/Cells/Cell1.html
The cache is discussed at the bottom of that page. The rest of the article is a very good write up on the cell architecture, and it's possibilities.
That article is full of errors and IMO is not a viable source of information.
However, to clarify, I need to correct both myself and cobra.
The 256KB of memory on each SPE is essentially a cache, however it has characteristics that seperate it from a conventional cache.
L1 and L2 cache are highly automated memory systems, which makes them simple to program for.
The only difference between L1 and L2 cache and the memory found on each SPE is that developers can dictate the way they wish the memory to be used on each SPE, increasing efficiency, however it operates much in the same manner as a cache would.
The report has many MANY errors in it, leading me to believe either it was written before the spec's of the Cell were released, or they are just using guess work.
For instance he states that the Cell has no cache, and only individual memory for each "APU" (even though they are referred to as SPE's).
He then states that each has it's own 128KB memory, when in reality it is 256KB.
Each SPE has 256KB of on-die memory allotted only to it, but instead of being used as conventional cache memory, this small area of high-speed storage is actually addressed almost like typical system RAM. The L1 cache memory found in conventional processors is highly automated, making it simple to program for but adding overhead. With the Cell processor, programmers can dictate exactly how they wish their software to use the 256KB allotment available to each SPE. This allows execution efficiency to be increased with good software design. It also allows better memory management and security from buffer overflows and other exploits.
Individual SPEs should be able to pass data to each other by storing it in specific areas of the system memory, forming a chain of processing units each performing a different operation on the data. Obviously this requires an extremely fast interface between the system RAM and the SPEs, which the Cell has in spades
More on this later.
Read that. It states that each SPE has 256KB of on-die memory. But it's not USED as "conventional cache", as it's much more flexible, however it serves the same purpose as a cache, considering it is possible for each SPE to communicate with eachother. The way it does this is by passing information along via the main L2 cache. Thus, since all of the memory works together, you can consider it a "total cache" since each SPE can pass along information to be used by eachother via system memory.
